Regviz

Alif Semiconductor /AE722F80F55D5AS_CM55_HE_View /DSI /DSI_PHY_RSTZ

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as DSI_PHY_RSTZ

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Alif Semiconductor/AE722F80F55D5AS_CM55_HE_View/DSI/DSI_PHY_RSTZ#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PHY_SHUTDOWNZ)PHY_SHUTDOWNZ 0 (PHY_RSTZ)PHY_RSTZ 0 (PHY_ENABLECLK)PHY_ENABLECLK 0 (PHY_FORCEPLL)PHY_FORCEPLL

Description

PHY Control Register

Fields

PHY_SHUTDOWNZ

When set to 0, this bit places the all D-PHY sub-blocks in power-down state.
PHY_RSTZ

When set to 0, this bit places the digital section of the D-PHY in the reset state.
PHY_ENABLECLK

When set to 1, this bit enables the D-PHY Clock Lane module.
PHY_FORCEPLL

When the D-PHY is in ULPS, this bit enables the D-PHY PLL.

Links

()

Register License

THIS SOFTWARE IS PROVIDED “AS IS”. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ALIF SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data